Electrical contact structures which extend through a semiconductor substrate are used, among other things, in microelectromechanical system components (MEMS, microelectromechanical system). Thus, such contact structures, also referred to as a through contact, through-connection, via (vertical interconnect access), or, in the case of a silicon substrate, as a through silicon via (TSV), are used, for example, to electrically connect various planes of the component to one another. These vertical through-connections allow a particularly space-saving design. In addition to simple rewirings, such through-connections allow individual components to be stacked on top of one another to form a so-called 3D package. Thus, for example, a sensor chip, a sensor cap, and an evaluation circuit (ASIC) may be put together in a space-saving manner in the form of a 3D package, the vertical electrical connections between the individual components being implemented with the aid of electrical through-connections. The term “MEMS 3D integration” is also used for the stacking and through contacting of individual components.
In implementing vertical contacts, the aim is to achieve contact structures having the smallest possible base area. At the same time, electrical through-connections should have the lowest possible volume resistance. To achieve this, very narrow holes having practically vertical walls are generally provided in the semiconductor substrate. This may be achieved using a customary trench method or a laser, for example. After the subsequent deposition of a thin insulating layer on the side walls and the base of the contact holes and opening of the insulating layer at the base of the contact hole, the holes are completely or partially filled with a metal. The filling is carried out either with the aid of a chemical vapor deposition (CVD) process or by depositing a metal layer with the aid of an electroplating process in combination with a previously deposited starting layer (seed layer).
Since in this concept the production of the through-connections takes place at the very end of the wafer process, these approaches are also referred to as “via-last.” A critical factor, among others, in these via-last approaches is the poor quality of the insulating layer, since the deposition of insulating material in the deep holes having a high aspect ratio may be achieved only in small thicknesses due to technical reasons. In addition, the oxides typically used as the insulating material have relatively poor oxide quality, since only deposition processes having a low maximum process temperature may be used at the end of the wafer processing. Due to the high aspect ratio of the holes, opening the insulating layer at the base of the holes is also particularly difficult. This is true in particular for thick insulating layers. Lastly, the deposition of a diffusion barrier, which is typically carried out prior to the metal deposition, is also very difficult technically due to the high aspect ratio and the depth of the holes.
In principle, through-connections may also be produced in earlier process stages. Thus, for example, in the middle of the wafer process a blind hole may be produced in the wafer and provided with an insulating layer and a barrier layer. After subsequent filling of the contact hole with a metal, a connection between the metallic filling and structures on the front side of the wafer may be established in a simple front-side process. Further front-side processes may subsequently take place. The filled blind hole is typically produced prior to the production of the metal printed conductors on the front side of the wafer, in the so-called metal back-end process.
At the end of the standard wafer process sequence, the wafer is ground on the back side, the grinding being made deep enough that the metallic filling of the blind hole is exposed. Lastly, an insulating layer is deposited on the back side of the wafer, and contact areas for the metal contact surfaces are opened in the insulating layer. Rewiring of the metal contacts may then also be carried out via a further metal layer which is deposited on the back side of the wafer. In these typical via-middle processes, differences in the thermal coefficients of expansion of the metals used and of the silicon substrate may result in damage to the previously applied TSV structures during the back-end processes. In addition, the grinding process has proven to be very difficult, since various materials such as silicon, oxide, barrier material, and metal must be ground at the same time; furthermore, metal smearing over the oxide insulating surface must be avoided to the greatest extent possible.